1. Field of the Invention
This invention relates to a microcomputer which enables data on the internal operation of an LSI and on the states of internal storage devices to be supplied to the outside.
2. Description of the Prior Art
Generally speaking, an important program for driving a microcomputer itself is stored in the ROM of the microcomputer. If the contents of this program can be displayed on a monitor for visual observation, it is possible to check or debug the contents on the monitor.
If application programs stored in a RAM and data stored in a register can also be displayed on the monitor, it is possible to check if these stored programs and data are correct.
Heretofore, a single-chip microcomputer with built-in OSD (On Screen Display) as shown in FIG. 25 has been available as a microcomputer which enables the contents of a storage device such as a ROM, RAM and register to be displayed on a monitor. In the figure, denoted at 1A is a single-chip microcomputer (referred to as "microcomputer" hereinafter) which incorporates a program counter 2, a register 3, a ROM 4 for storing programs, a RAM 5 for storing data required for processing, a display contents latch unit 7 including a plurality of latch circuits for latching digital values which appear on an address bus 9 and a data bus 8, and a display controller 6 for converting the contents of the display contents latch unit 7 into character and graphic data and supplying the converted data to an external display device. The display contents latch unit 7, the register 3, the ROM 4 and the RAM 5 are connected to the data bus 8 and the address bus 9. The directions of the arrows of the data bus 8 and the address bus 9 indicate the directions of the inputs and outputs of signals (address data and data) on these buses. Denoted at 11 is a central processing unit (CPU) for controlling the buses 8 and 9 internal to the microcomputer 1A, which generates a bus timing control signal 12 to the outside of the microcomputer 1A. The program counter (PC) 2 is connected to the CPU 11 and stores the address of an instruction being currently executed. Denoted at 13 is the display output of the display controller 6, 14 an address bus output signal for supplying the contents of the address bus 9 within the microcomputer 1A to the outside of the microcomputer 1A, and 15 a data bus output signal for supplying the contents of the data bus 8 within the microcomputer 1A to the outside of the microcomputer 1A. Reference numeral 16 represents the synchronizing signal of a TV screen to be applied to the display controller 6 from the outside of the microcomputer 1A. Since output signals 12, 14 and 15 are concurrent with one another, the microcomputer 1A uses a multi-axis cable and is provided with a large number of pins as terminals.
A description is subsequently given of the operation of this microcomputer. The register 3, the ROM 4 and the RAM 5 are each connected to the data bus 8 and the address bus 9 and information is transmitted under the control of the CPU 11. FIG.26 is a timing chart of an example of the operation. Addresses and data to be written to or read from the program counter 2, register 3, ROM 4 and RAM 5 appear on the address bus 9 and the data bus 8 on a time-division basis, and are specified by the bus timing control signal 12.
A reference clock .phi. signal 12a, a SYNC signal 12b, a WR signal 12c (bar indicates that the signal is active when it is at a low level), and an RD signal 12d shown in FIG. 26 are supplied from the CPU 11 as the bus timing control signal 12. A leading address 23a of an instruction code which appears on the address bus 9 is indicated by a fall in the SYNC signal 12b and is the contents of the program counter 2 supplied from the CPU 11. The instruction OP code, LDM, of the program counter 2 shown in FIG. 32 is an instruction shown at the bottom of the figure. In this case, data 25 appearing on the address bus 9 and to be written to the RAM 5 at an address 24 is DATAx which is written upon a rise in the WR signal 12c.
ADL refers to the low-order 8 bits of an address and ADH the high-order 8 bits of the address. The clock .phi. signal is the reference clock signal of an instruction, the SYNC signal is a timing signal indicating the leading address of an instruction code, the WR signal is a write timing signal for writing data to the register 3 and the RAM 5, and the RD signal is a read timing signal for reading data from the register 3, the ROM 4 and the RAM 5. The display contents latch unit 7 is connected to the address bus 9 and the data bus 8 as is the RAM 5 so as to enable data to be written from and read out to the data bus 8 by the CPU 11. The written (latched) contents of the display contents latch unit 7 are applied to the display controller 6 which in turn converts the output data of the display contents latch unit 7 into character and graphic data and supplies the converted data to the outside of the microcomputer 1A as the display output 13 in response to the synchronizing signal 16.
Meanwhile, there are two methods for supplying the contents of the register 3, ROM 4 and RAM 5, and the contents 23a of the program counter 2 through the CPU 11 to the outside of the microcomputer 1A. One of the methods is to supply a bus timing control signal 12, address bus output signal 14, and data bus output signal 15 to the outside of the microcomputer 1A and identify these contents according to the timing relationship among these three signals. In this first method, there are a large number of pins on the microcomputer 1A as shown in FIG. 27, and wiring becomes complicated for debugging. Furthermore, an additional monitor c connected to a debugger d is required for debugging. In this case, a program for instructing debugging is an application program L as shown in FIG. 28.
Denoted at letter a in FIG. 27 is a TV monitor connected to the microcomputer 1A. A timing output line 12, display output line 13, address output line 14 and data output line 15 extending from a large number of output signal pins provided on the microcomputer 1A are connected to the debugger d.
The second method is to transfer the contents of the program counter 2, register 3, ROM 4 and RAM 5 to the display contents latch unit 7 via the data bus 8 by means of software and identify these contents from the display output 13. FIG. 29 shows a TV monitor a connected to the microcomputer 1A, employing this second method.
In this case, although the number of output signal pins of the microcomputer 1A does not increase, a debug instruction program is required, which includes a program W for reading a test switch (test SW) and transfer programs i to k for transferring the contents of the RAM 5 to the display contents latch unit 7, thereby increasing the program volume. This means that an external storage device g for storing the debug instruction program needs to be installed on a substrate f, or the ROM 4 is occupied with the debug instruction program. In addition, the CPU 11 must perform transfer processing Z (processing of transferring the contents of the RAM 5 specified by the test switch to the display contents latch unit 7) according to the transfer programs i to k, thereby increasing the load on the CPU 11.
In other words, the method in which the signal output pins are connected to the debugger requires no special software for debugging because of hardware processing, but takes a lot of time and labor for preparation for observation such as wiring.
On the other hand, the second method which employs software processing requires the transfer programs i to k, resulting in an increased program volume and a greater load on the CPU 11 (transfer processing Z).
The expression "reading test switch (W)" used in FIG. 30 means a read operation of a program for switching the screen of the TV monitor a from a normal mode to a test mode when the power switch, channel switch and volume switch of a TV are depressed at the same time and a program which enables a RAM (A) to be specified by depressing the channel switch and a RAM (B) to be specified by depressing the volume switch thereafter.
Therefore, it is possible to instruct debugging by specifying a RAM to be monitored with the test switch and transferring contents to be debugged to the display contents latch unit 7 by means of the CPU 11.
Besides the microcomputer with built-in display controller described above, a microcomputer with built-in D/A converter is commonly known. An example of this microcomputer with built-in D/A converter is described below with reference to FIGS.31 to 36.
FIG. 31 is a block diagram of the internal configuration of the single-chip microcomputer with built-in D/A converter. In the figure, a program counter 2, register 3, ROM 4 and RAM 5 are incorporated in the microcomputer 1B, and connected to the data bus 8 and the address bus 9. The directions of the arrows of the data bus 8 and the address bus 9 show the directions of the inputs and outputs of signals (address data and data) on these buses. Denoted at 111 is a bus timing controller for controlling the internal buses 8 and 9 of the microcomputer 1B, and 116 an interrupt controller for controlling interrupt processing in the microcomputer 1B.
Denoted at 16a and 16b are D/A converters incorporated in the microcomputer 1B, which receives inputs 10a and 10b, and supplies outputs 13a and 13b to the outside of the microcomputer 1B. Reference numeral 118 represents an internal state latch unit for selecting the internal states of the microcomputer to be monitored and temporarily storing the selected states, 19 refers to internal state latch unit outputs for supplying the selected ones out of a plurality of the internal states, 120 an internal state monitor/selector for selecting the internal states to be monitored, whose output 21 is applied to the internal state latch unit 118 and a D/A input selector 22 to be described below. Reference numeral 12 represents the output of the bus timing controller 111 which is applied to the internal state latch unit 118, and 22 a D/A input selector for selecting two of the internal state latch unit outputs 19 and supplying the selected outputs to the D/A converters 16a and 16b.
FIG. 33 shows exemplary circuits of the D/A converters 16a and 16b, the internal state monitor/selector 120 and the internal state latch unit 118.
A description is subsequently given of the operations of these units. Two of the internal states to be monitored are selected by the internal state monitor/selector 120. The select control signal controls the internal state latch unit 118 through the output 21 of the internal state monitor/selector 120. The internal state latch unit 118 selects two from among the states of the program counter 2, register 3, ROM 4 and RAM 5 according to information from the address bus 9, the data bus 8 and the bus timing control signal 12 and temporarily stores the two. As for the specification, states at two specific addresses in different blocks among the program counter 2, register 3, ROM 4 and RAM 5 may be selected, or states at two specific addresses in a single block (for example, RAM) may be selected.
A description is given of the exemplary operation of the internal state latch unit 118 with reference to FIG. 32. In the figure, .phi., SYNC, WR and RD represent the bus timing control signals 12a to 12d, ADDR the contents of the address bus 9 and DATA the contents of the data bus 8. In this example, the contents of the program counter 2 and the contents (to be written) of the RAM 5 at an address ADL (low-order address) are selected by the internal state monitor/selector 120. The internal state latch unit 118 latches the value (contents 27a of (PC), contents 27b of (PC+3)) of the program counter 2 which appears on the address bus 9 upon a fall in the SYNC signal, and temporarily stores and supplies LATCH SYNC as one of the internal state latch unit outputs 19. Upon a rise in the WR signal, the internal state latch unit 118 also latches the contents DATAx 26 to be written to the RAM 5 at an address ADL, which appear on the data bus 8 when the value of the address bus 9 becomes the address ADL, and temporarily stores and supplies LATCH DATA as another internal state latch unit output 19. In this example, the D/A input selector 22 selects under the control of the internal state monitor/selector output 21 the above two, that is, the state of the program counter 2 (LATCH SYNC) and the state of the RAM (LATCH DATA) at the address ADL among from the states of the internal state latch unit outputs 19, and supplies these as the two D/A converter inputs 10a and 10b, respectively. The two D/A converters 16a and 16b convert these inputs 10a and 10b (digital values) into analog values and supplies the analog values to the outside of the microcomputer as the D/A converter outputs 13a and 13b, respectively.
A description is subsequently given of the operation of the microcomputer when a program is actually executed.
FIG. 34(a) and (b) are flow charts of a sample program. In the main routine (MAIN) of FIG. 34(a), the internal state monitor/selector 120 is set so that the state of the program counter 2 is supplied as the D/A converter output 13a and the contents of the RAM 5 at an address "0000" are supplied as the D/A converter output 13b (step 28). Thereafter, a predetermined time period is awaited (step 29), and the contents of the RAM 5 (labelled COUNTER) at the address "0000" is incremented by one (step 30). These steps 29 and 30 are looped eternally (step 29.fwdarw.step 30.fwdarw.step 29 . . . ). On the other hand, in the general interrupt processing (INT) of FIG. 34(b), the contents of COUNTER are reset to "0" each time an external interrupt input 17 is detected as shown in FIG. 34(b) (step 31). When the above-mentioned programs and COUNTER data are allocated to the addresses of MEMORY MAP shown in FIG. 35 and the programs are executed, waveforms as shown in FIG. 36 are output as the D/A converter outputs 13a and 13b. Reference numeral 32 represents a variation range of COUNTER (address 0000+i), 33 an address range of a main routine (F000 to F020), and 34 an address range of interrupt processing (FF00 to FF20). It is easily observed from the outputs 13a and 13b of the D/A converters 16a and 16b on an oscilloscope that each time an interrupt is generated, an address jump occurs and the contents of COUNTER are cleared.
Since the single-chip microcomputer with built-in display controller of the prior art is constructed as described above, there have been two methods for supplying data on the internal states of the microcomputer including the program counter to the outside: the first method is to supply the address bus signal, the data bus signal and the bus timing control signal, and the second method is to transfer desired data to the display contents latch unit according to the instruction of software and identify the data from the output of the display controller.
However, according to the first method, a large number of signal pins are required, thus imposing a volume problem on a high-density small-sized single-chip microcomputer which has a limitation on the number of pins. Since data are obtained directly from the address bus signal, the data bus signal and the bus timing control signal, and not from the output of the display controller for the observation of the internal states, the measured signals are binary pulse signals and a sequence of pulses must be observed. Therefore, it is difficult to identify the internal states of the microcomputer. In other words, since use cannot be made of the advantage of the display controller at all, the microcomputer cannot be used effectively.
The second method has the problem that the program volume is increased as additional software is used for supplying the contents to the outside of the microcomputer on a regular basis.
In other words, to instruct debugging, it is necessary to transfer the contents to the display contents latch unit by means of the CPU. For this purpose, the transfer programs i to k for performing the transfer processing Z of FIG. 30 must be added, resulting in a huge program volume and a greater load on the CPU due to the transfer processing Z.
The microcomputer with built-in D/A converter shown in FIGS. 31 to 36 does not comprise means for instructing debugging. Although this means does not require the transfer programs i to k of FIG. 30, means for setting the contents to be debugged in the internal state monitor/selector 120 is required instead. Furthermore, since an analog signal is supplied from the microcomputer, it is difficult to observe the contents using an oscilloscope or voltmeter when characters or accurate numerical values are to be displayed on a monitor. D/A converters which occupy a large space are required for observation. Since an apparatus (such as an oscilloscope and voltmeter) separate from an application apparatus is used for observation and display when an application program is debugged, it is difficult to observe both the operation state of the application apparatus and the internal states (such as a RAM value) of the microcomputer simultaneously, and it is necessary to prepare another measurement instrument for observation. Since at least one output is required for each observation data, a large number of D/A converters and output terminals are needed for a large number of observation data. The capacity of the D/A converter is limited to 10 bits from a viewpoint of semiconductor technology when it is incorporated into a microcomputer. Therefore, when internal data consists of many bits (plural bits), observation is difficult.